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Lena/Sep 2016: Difference between revisions
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The 32-bit version performs as good as the hardware lock-in. For some reason, the hardware lock-in PSD noise increases for higher frequencies, and for the 32-bit FPGA lockin it doesn't. The 32-bit version has 50 times smaller noise level than the 16-bit version.
NoiseCompare(day='2016.08.31', run='14', noise='02', bs=1, Chan=1, direc='Y', label='Elec, Hardware demod/filter', ver='v16', fmax=200, radresp=0, calib=2e-06, Ipr=0.0001, psn=0);
NoiseCompare(day='2016.08.31', run='00', noise='02', bs=1, Chan=1, direc='Y', label='Elec, LV demod/filter 16 bit', ver='v16', fmax=200, radresp=0, calib=2e-06, Ipr=0.0001, psn=0);
NoiseCompare(day='2016.09.16', run='32', noise='02', bs=1, Chan=1, direc='Y', label='Elec, LV demod/filter 32 bit', ver='v16', fmax=200, radresp=0, calib=2e-06, Ipr=0.0001, psn=0);
[[File:Electronic noise comparison 2016 09 16.png]]
The data is acquired at the sampling rate of 500 ksps, and then averaged to approximately 200 sps (final FPGA filter has fc=180 Hz). This should improve the bit resolution by a factor of Sqrt(500 ksps/200 sps) = Sqrt(2500) = 50 (6-7 bits).
The estimated gain was 25 μV/fT. The LSB voltage step is 300 μV, the effective LSB after averaging should be 300/50 = 6 μV = 0.25 fT.
==== Filtering/digitization ====
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