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--[[User:Zjsimmons|Zjsimmons]] ([[User talk:Zjsimmons|talk]]) 14:14, 13 May 2014 (CDT)
Have seen a fragile lock:) Despite Multisim showing gain should be -20 dB at 400 Hz, it still seems prone to 420Hz (resonance) oscillation. Issues:
* Switch to put bypass resistor to kill integrator when not locked seems important. Otherwise integrator will chug away and rail at some point. I'm also thinking having a low noise op amp for that stage should help prevent gain on op amp error for example. -added the switch.
* Should we use a different piezo with a higher resonance frequency?
* Piezo DC offset should only be positive- I changed this.
* Lock seems ok. Also added a 100nF cap on the output/input to the sum with DC offset as a passive low pass filter. I'm sure this could be improved but i think we should try it for now and see what happens.
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