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--[[User:Zjsimmons|Zjsimmons]] ([[User talk:Zjsimmons|talk]]) 14:14, 13 May 2014 (CDT)
Have seen a fragile lock:) Despite Multisim showing gain should be -20 dB at 400 Hz, it still seems prone to 420Hz (resonance) oscillation. Issues:
* Switch to put bypass resistor to kill integrator when not locked seems important. Otherwise integrator will chug away and rail at some point. I'm also thinking having a low noise op amp for that stage should help prevent gain on op amp error for example.
* Should we use a different piezo with a higher resonance frequency?
* Piezo DC offset should only be positive.
--[[User:Zjsimmons|Zjsimmons]] ([[User talk:Zjsimmons|talk]]) 22:51, 12 May 2014 (CDT)
Spent today trying different locking gain stage configurations, tried adding an additional stage to increase gain. Discovered error signal was not being properly added to DC offset, this seems to be corrected but two problems have cropped up:
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