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Lena/Aug 2016: Difference between revisions
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→Issues with the data acquisition
ElenaZhivun (talk | contribs) |
ElenaZhivun (talk | contribs) |
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# In the demodulation circuit diagram: two 16-bit integers are multiplied and produce a 32-bit integer, which is then scaled back to 16 bit. The original v16 program scales is by a factor of 2^-14, while it really should be 2^-16, to pick out the high word of the product.
# In the data sampling: the FPGA always acquires the data at 500ksps. The data is demodulated and filtered at 250ksps, and both these frequencies are hardwired. Sampling rate set by the host VI only sets the rate at which the data is send to the computer. This rate is smaller than the data acquisition rate, and the VI seems to discard the other samples, rather than average them.
# The ADC with the 16-bit resolution and ±10V input range is only sufficient to resolve ~10-20 fT at 15 μV/fT gain
# Filter cutoff for the low-pass filters is 250 Hz, which is very small compared to the fs = 500ksps, which results in the filter coefficients differ by 4 orders of magnitude, and the data is only 16 bits. Precision errors might happen.
# We are using Butterworth filter, which does not have a flat phase response. Having the flat phase response is very important to avoid distortions in the signal in the time domain. We should use Bessel filter instead.
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