150
edits
Lena/Sep 2016: Difference between revisions
Jump to navigation
Jump to search
→09/23/2016
|
I don't see any DC offset on the Z-mode outputs. The chirps are always output without the DC offset, but sometimes after the VI finishes the chirp voltage is set to some DC level. It happens once in 2-3 runs, and the voltage is proportional to the amplitude of the chirp. I think it's because the "FPGA output zeroes" subVI is not doing that, and the DC level is a part of the next chirp.
Modified the "Send Chirps" subVI so that "chirp?" variable is only written once at the first call, that solved the problem.
| |||