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Lena/Sep 2016: Difference between revisions
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We (I and Zach) are thinking that this might be because there is some random voltage on the Z-mode outputs while the chirps are running. I connected the FPGA outputs to the scope to see what they are outputting. I also recompiled the FPGA firmware to make all 4xint16 ↔ int64 converters compiled as pre-allocated clones, because I thought that maybe the pool of them wasn't large enough for the FPGA to function. (That didn't change anything.)
I don't see any DC offset on the Z-mode outputs. The chirps are always output without the DC offset, but sometimes after the VI finishes the chirp voltage is set to some DC level. It happens once in 2-3 runs, and the voltage is proportional to the amplitude of the chirp. I think it's because the "
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