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Lena/Oct 2016: Difference between revisions
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→Adding an anti-aliasing filter to the polarimeter
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[[File:MagRun2PSN 2016.09.27 R20N020304 Chan1Y.png|300px]]
=== Ripples ===
There are some ripples on the magnetometers calibration. They might be caused by the windowing.
=== Adding an anti-aliasing filter to the polarimeter ===
In order to run the data acquisition at a smaller rate, we can place a hardware anti-aliasing filter on the differential polarimeter boards. This would take the computational load off the digital system and relax the requirements on how fast we acquire the data. Mike suggests replacing adding an active two-pole filter at the output of the polarimeter board. We can place a quad OP140 on the board instead of the dual version. The filter design is described in Horowitz and Hill in CH5.07 page 274. We would need to try different filters to see which one works best for our signal.
=== Expanding the number of channels ===
I checked the National Instruments website to see what equipment we might need to expand the number of channels. Each channel requires two analog inputs (Differential and sum polarimeter signals) and two analog outputs (chirp/calibration signal and Z-modulation). We could save one AI by only recording the difference signal, or add one AO if we want to modulate the field along two axes and get three-axial output. We potentially want a digital feedback on X, Y fields as well.
There are two main approaches we can use. The first approach is to have multiple FPGAs, each one controlling a set of four magnetometers. The cheapest NI FPGA (7851R) costs $2.8k, equating is $700/channel. The drawback is that the FPGA only has 8 analog inputs and 8 analog outputs, and there are no analog outputs free for the feedback signals. There are still free digital outputs that the FPGA can use to talk to an Arduino over SPI or something similar. Using FPGAs will result in the fastest feedback with proper timing. We don't have the requirements for the feedback to be fast (its band is DC-0.5 Hz as of now) With the signal normalization the FPGA is already close to its limit of slices.
The second approach is to use a PXI rack with stacks of ADCs and DAQs. The advantage is that we can add DAQs very easily by adding new boards. We could use a dedicated real-time controller to process the data, and if both DAQs and ADCs support NI DAQmx then the real time controller is not really needed. These boards have their own controllers that ensures timing, and the data processing can be done on the host computer. Each sensor running at 20 kHz with 18-32 bit resolution should produce around 1 MBit/second of data, which is very manageable.
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